1. Field of the Invention
The present invention relates to an image display such as liquid crystal display and, more particularly, relates to an image display including internal wiring for inputting a signal and a power supply from an external circuit to a driving IC for supplying a signal to a scanning line or a signal line of a display panel on an insulating substrate composing the display panel. The invention also relates to a method of manufacturing such image display.
2. Background Art
Under the background an increasing demand for reliable and less expensive medium-sized or small-sized image displays to be used for a car navigation system and so on, it is a recent trend that a driving IC of a display panel is mounted in a package area on an insulating substrate forming an image display. This is so-called a “Chip On Glass (hereinafter referred to as COG) Packaging” employed in many cases.
In this COG package, a signal and a power supply are inputted to the driving IC through a conductive film (hereinafter referred to as internal wiring) formed in the packaging area on the insulating substrate. In designing a pattern of this internal wiring, it is essential to lay out internal wiring having a resistance value that does not cause any abnormal driving IC output in a wiring area restricted and determined depending upon the size of the image display.
One of conventional image displays having an internal wiring for inputting a signal and a power supply to a CGO-packaged driving IC mounted is hereinafter described as an example of a liquid crystal display in which a thin film transistor (hereinafter referred to as TFT) is mounted as a switching element.
FIGS. 15, 16, and 17 respectively show the conventional liquid crystal display having the internal wiring for inputting a signal and a power supply to the CGO-packaged driving IC mounted on a TFT array substrate. FIG. 15 is a plan view showing a part (in the vicinity of the driving IC packaging area) of the conventional liquid crystal display, FIG. 16 is a sectional view taken along the line E-E in FIG. 15, and FIG. 17 is a sectional view showing a manufacturing process taken along the line E-E in FIG. 15.
In the drawings, reference numeral 1 is a TFT array substrate forming the liquid crystal display, numeral 2 is an opposed substrate being opposed to the TFT array substrate 1 and holds a liquid crystal material between the TFT array substrate 1 and the opposed substrate 2. Numeral 3 is a display area of the liquid crystal display, numeral 4 is a driving IC, numeral 5 is a driving IC output terminal, and numeral 6 is a driving IC input terminal. Numeral 7 is wiring for connecting the driving IC to a scanning line (gate wiring) or a signal line (source wiring), numeral 8 is internal wiring for inputting a signal and a power supply from an external circuit to the driving IC, and numeral 9 is a connecting terminal on the substrate side where a signal and a power supply from the external circuit are supplied. Numeral 11 is an insulating substrate (glass substrate), numeral 12 is a first insulating film (gate insulating film), and numeral 13 is a second insulating film (passivation film).
A manufacturing process is hereinafter described. First, a metal such as Cr to serve as a first conductive film is accumulated 0.1 to 1.0 μm through sputtering on the insulating substrate 11 such as glass substrate and patterned by photoengraving and etching. Thus the internal wiring 8 and a gate electrode and gate wiring (not shown) of a TFT are formed (FIG. 17(a)).
Next, the first insulating film (gate insulating film) 12, a non-doped amorphous semiconductor film, and an amorphous semiconductor film where an n-type impurity is doped are successively accumulated through CVD. The non-doped amorphous semiconductor film and the amorphous semiconductor film where the n-type impurity is doped are patterned by photoengraving and etching, whereby a semiconductor layer and a contact layer (not shown) are formed. Furthermore, a metal such as Cr to serve as a second conductive film is accumulated 0.1 to 1.0 μm through sputtering and patterned by photoengraving and etching. Thus a source/drain electrode and source wiring (not shown) of the TFT are formed. At this stage, only the first insulating film 12 remains in the portion where the internal wiring 8 is formed (FIG. 17(b)).
Subsequently, the second insulating film (the passivation film) 13 is accumulated through CVD (FIG. 17(c)).
Then, contact holes (not shown) are formed on the first insulating film (gate insulating film) 12 and the second insulating film (passivation film) 13. Finally, ITO to serve as a transparent conductive film is accumulated through sputtering so as to cover the contact holes and patterned by photoengraving and etching, whereby a display electrode (not shown) connected to the drain electrode through the contact hole and wiring (not shown) connecting the first conductive film and the second conductive film through the contact hole are formed. Thus, a TFT array substrate is formed through the foregoing process.
The internal wiring for inputting a signal and a power supply to the driving IC is classified into a signal system and a power supply system. Approximately ten in total of wiring are laid down for shift resistor clock, wiring for start pulse, etc. in the signal system, and for a level shifter, an output buffer power supply VGG, a ground power supply VEE, a logic power supply VDD, etc. in the power supply system. A standard resistance value of each internal wiring is not larger than several kΩ in the case of the signal system, and not larger than several hundreds Ω in the case of the power supply system. A signal and a power supply to be inputted to the driving IC are inputted from external circuit through a connecting terminal on the TFT array substrate.
As described above, in the case of laying out the internal wiring for inputting a signal and a power supply to the COG-packaged driving IC mounted in the packaging area on the TFT array substrate, a wiring width of each internal wiring is estimated based on the resistance value that does not cause any abnormal driving IC output, and width of the COG packaging area is restricted by external size of the display panel depending upon the product specification. Therefore a problem exists in the conventional liquid crystal display that it is necessary to enlarge the external size of the display panel in order to obtain a resistance value of the internal wiring that satisfies the display properties. Another problem exists in that in a case where external size of the display panel takes priority to the resistance value of the internal wiring, increase in internal wiring resistance value gives a negative influence on the display properties.